//fifo_wr模块

module fifo_wr(
	input				sys_clk		,
	input				sys_rst_n	,
	
	input				wrempty		,	//写空信号
	input				wrfull		,	//写满信号
	output	reg[7:0]	data		,	//写数据
	output	reg			wrreq		,	//写请求
	
	);
	
reg	[1:0]				flow_cnt	;	//状态流转信号

//向fifo写入数据
always	@(posedge sys_clk or negedge sys_rst_n) begin
	if(!sys_rst_n)	begin
		flow_cnt	<= 2'b0;
		data 		<= 8'b0;
		wrreq		<= 1'b0;
	end
	else begin
		case(flow_cnt)
			2'd0:	begin
				if(wrempty)	begin	//写空信号
					wrreq <= 1'b1;
					flow_cnt <=flow_cnt + 1'b1;
				end
				else	
					flow_cnt <= flow_cnt;
			end
			2'd1:	begin
				if(wrfull)	begin	//写满信号
					wrreq <= 1'b0;
					data <= 8'b0;
					flow_cnt <= 2'b0;
				end
				else	begin		//没写满的时候 写请求继续拉高 继续写入数据
					wrreq <= 1'b1;
					data <= data + 1'b1;
				end
			end
			default:	flow_cnt <= 2'd0;
		endcase
	end
end
	
	
	
endmodule